The memory wall is no longer a theoretical limit. It is the daily tax on every frontier inference workload.
Volantis just raised $88 million to attack it with light.
The bottleneck that scaled with the models
Modern AI accelerators compute far faster than memory systems can feed them. The result is well documented: processors sit idle waiting for weights and activations. High-bandwidth memory stacked next to the GPU die is the industry’s current answer. It buys capacity, but electrical reach stays short—typically a few millimetres. Flagship designs therefore pair roughly eight HBM stacks per GPU. Beyond that, packaging complexity and thermal density explode.
The arithmetic is unforgiving. As models grow from hundreds of billions to multiple trillions of parameters, the working set no longer fits in local HBM. Bandwidth, not FLOPS, becomes the binding constraint. Every additional millimetre of copper costs energy and limits how many memory chiplets can sit in a uniform-latency domain. That is the memory wall in practice.
Volantis frames the problem differently. Volantis extends the reach of the interconnect itself, instead of packing more memory ever closer to the compute die. Optical links travel farther at lower energy per bit. That extra distance lets one GPU address far more memory chips—company materials claim more than 220 memory chiplets in a single uniform-latency pool.
Optical fabric, not another silicon-photonics interposer
The technical centrepiece is what Volantis calls the optical fabric. Key design choices stand out from earlier photonic efforts:
- Custom integrated micro-VCSELs instead of external lasers
- No traditional optical fibre—waveguides integrated into the interposer
- Gallium-arsenide laser platform, deliberately avoiding indium-phosphide supply constraints
- Claimed end-to-end energy below one picojoule per bit
- Thermal stability above 95 °C and bit-error rate targets under 1e-12 at wafer scale
VCSELs are already mass-produced for smartphone facial recognition. Volantis treats that existing GaAs supply chain as a manufacturing advantage instead of a research risk. The reach of the optical waveguides is specified beyond 200 mm—orders of magnitude farther than electrical links that typically stop at 2–5 mm. That distance is what unlocks the higher memory-chip count.
The first system, A-1, is specified at roughly 10 TB of memory, 240 TB/s aggregate bandwidth, a 20 kW power envelope and a 15U form factor that fits existing racks. Target delivery window: 2027. Company materials also list 10 TB/s of off-wafer IO bandwidth. These remain design goals; no independent measurements from a running system have been published.
Team that already shipped the hard parts
The pedigree is unusually dense for a Series A. CEO Tapa Ghosh is a Thiel Fellow and former Y Combinator founder. CTO Roy Meade previously led Micron’s high-bandwidth memory programme and served as VP of engineering at Ayar Labs. Packaging leadership includes engineers who shipped the industry’s first CoWoS product at NVIDIA. Laser engineering draws from the team that took high-volume tunable VCSELs to production.
That combination matters. CoWoS, HBM and early co-packaged optics were all once considered high-risk integration challenges. The same people are now applying that experience to a wafer-scale optical interposer. Backers include Lachy Groom and Abstract Ventures as co-leads, plus John Doerr, Sam Altman, Jeff Dean, Dylan Patel, Naveen Rao and others. Total capital disclosed after the round sits near $97 million.
What the numbers actually claim
Company targets are ambitious: models exceeding 20 trillion parameters at up to 10 000 tokens per second per user. Those are design goals, not measured results from a running system. Company materials illustrate the point with coding-agent workloads that finish in minutes instead of half an hour. If the bandwidth and latency numbers hold, the economic impact is straightforward—lower cost per token from both higher utilisation and the ability to use less expensive off-chip memory.
Comparable photonic efforts (Lightmatter, Ayar Labs, Celero, CScale) have largely focused on chip-to-chip or rack-scale interconnect. Volantis is explicitly optimising the chip-to-memory path, which moves more than 100× the data volume over much shorter distances. That distinction matters for both energy and packaging constraints. It also explains why the company emphasises micro-VCSELs and the absence of external lasers: the power and density budgets at the memory interface are tighter than at the network edge.
Competitive landscape and open questions
Several risks remain unclosed. First-customer delivery is still a year away. Packaging a wafer-scale optical interposer at commercial yield is non-trivial. Thermal management of thousands of micro-VCSELs on the same substrate has not been demonstrated in public data. And the competitive response from NVIDIA, AMD and the major memory vendors is unknown—none of them are standing still on advanced packaging or optical I/O.
Supply-chain choice is a double-edged sword. GaAs VCSELs are mature, yet the volumes required for AI accelerators dwarf current smartphone demand. Scaling that capacity without price spikes will be a parallel execution problem. Meanwhile, other photonics startups continue to raise capital for adjacent pieces of the stack. The market will ultimately decide whether a memory-centric optical fabric is the highest-impact place to apply the technology.
Why the chip-to-memory path is different
Most photonic interconnect work in data centres has targeted the network edge or the GPU-to-GPU fabric inside a rack. Those links carry high aggregate bandwidth but relatively modest data volumes per connection. The memory interface is the opposite problem: enormous data volume over very short distance, with strict latency and energy budgets. Volantis is optimising for that regime. The optical fabric is designed so that memory capacity and bandwidth scale together as more chiplets are added, instead of forcing a fixed capacity-bandwidth product set by the electrical package.
That architectural choice also changes the cost structure. If memory no longer has to sit in the most expensive advanced-packaging real estate next to the compute die, system designers can mix higher-capacity, lower-cost memory technologies while still keeping them inside a low-latency domain. The company claims this pooling effect is a primary mechanism for reducing cost per token.
What success would actually look like
Success is not binary. Even if the full 220-chiplet, 240 TB/s vision slips, a working optical interposer that delivers 5–10× the memory bandwidth of today’s HBM stacks at comparable or better energy would still reshape the inference economics for large models. The coding-agent example is illustrative, not definitive: the real prize is any workload that is currently memory-bound, not compute-bound. That set is growing as context windows expand and multi-agent systems keep more state in memory.
For operators, the decision will hinge on measured tokens-per-watt and tokens-per-dollar numbers once hardware exists. For the rest of the industry, the signal is simpler: the memory wall is no longer accepted as an immutable physical limit. Capital and talent are now allocated to dissolving it with light.
Forecast
If Volantis hits its 2027 delivery window with bandwidth and energy numbers close to the claimed targets, the company becomes a serious contender in the next wave of inference infrastructure. Even partial success—say, 5–10× effective memory bandwidth at acceptable power—would force every major accelerator vendor to re-evaluate the electrical HBM roadmap.
The more likely near-term outcome is a longer validation cycle and selective hyperscaler pilots instead of immediate volume deployment. Either path, the memory wall is now a funded research programme with a clear optical thesis and a team that has already shipped comparable integration challenges. That combination is rare at Series A.
Primary sources: Volantis company announcement and technical materials, Reuters coverage of the round (1 Oct 2026), independent technical summaries from Chip Dispatch, HPCwire and TDisrupt.